DATA (PIXEL) STREAM INTERFACE
The Data Stream interface is based on the AMBA AXI4-Stream protocol. On the source side, this interface provides the user logic with images acquired from a CoaXPress Device (for example a CoaXPress camera). On the destination side, the Data Stream interface transfers the resulting images/data generated by the user logic to the PCI Express DMA Back-End channel.
DDRA4 MEMORY INTERFACE
The DDR4 Memory interface is based on the AMBA AXI4 protocol.
MEMENTO EVENT INTERFACE
The Memento Event interface allows the User Logic to send timestamped events to the Memento Logging tool with a precision of 1 μs. Along with the timestamped event, two 32-bit arguments are reported in Memento.
The Control/Status interface allows the user to read and write registers inside the user logic via the Coaxlink Driver API.
The Coaxlink CustomLogic SDK is delivered with a reference design intended to be used as a template. The reference design exposes all interfaces available to the user. It is a Xilinx Vivado project with the following functional block diagram:
Using CustomLogic does not require any additional hardware. The 3613 JTAG Adapter Xilinx for Coaxlink (available free of charge from AMD-Xilinx) allows connecting the Xilinx programmer to the Coaxlink FPGA for debugging purposes.
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