IP 核的第一个组件是顶层设计。它是外部硬件（成像器件、传感器、GigE PHY）和 FPGA 内部数据处理之间的接口。我们提供此模块的 VHDL 源代码，可以针对自定义硬件进行改编。
帧缓冲区核连接到 FPGA 供应商特定的内存控制器。帧缓冲区允许帧缓冲和图像分区。这对于实现数据包重发功能必不可少。
Some parts of the design are compiled files only (for example the GigE Vision control protocol library), while other parts as source code. The design framework comes with all the necessary design files and cores, Vivado or Quartus project files. It is configured either as a GigE Vision camera system with an optional CMOS imager, or as an embedded GigE Vision host (receiver). This system is used as a reference design and evaluation board. The reference design uses the AMD or Intel development tools (not in the scope of delivery).
GigE Vision IP 核描述
GigE Vision is a standard communication protocol for vision applications based on the well-known Ethernet technology. It allows easy interfacing between GigE Vision devices and PCs running TCP/IP protocol family. Sensor to Image offers a set of IP cores and a development framework to build FPGA-based products using the GigE Vision interface. Due to the speed of GigE Vision, especially at speeds higher than 1 Gb/s, senders and receivers require a fast FPGA-based implementation of the embedded GigE core. GigE Vision cores are compatible with AMD 7 Series devices (and higher) and Intel Cyclone V devices (and higher).
参考设计的视频采集模块可模拟具有测试图案生成器的相机。此模块以 VHDL 源代码形式提供，须由相机设计中的传感器接口和像素处理逻辑代替。
GigE 数据包组包器将所有数据发送到以太网 MAC，并实现高速 GigE Vision 流传输协议 (GVSP)。
用于 GigE Vision 的 MVDK 机器视觉开发套件
Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. It supports GigE Vision host and device reference designs for various Enclustra FPGA modules with Intel and AMD FPGAs.