Coaxpress Frame Grabbers
Camera Link Frame Grabbers
Non-Standard AnalogFrame Grabbers
Standard PAL/NTSC/1080Pvideo capture cards
GigE Vision, USB3 Vision, CoaXPress
IMX Pregius IP Cores
Machine Vision Development Kit
Image AnalysisSoftware Tools
Evaluation andprototyping tool
IP core for Sony Pregius Sub-LVDS image sensors
The IMX sensor itself can be used in free running mode or in slave mode using the core’s timing and trigger generator. An SPI-based control interface enables sensor conﬁguration, following the correct conﬁguration timing.
The IMX Pregius from Sony is a series of widely used, high quality CMOS image sensors. S2I’s IMX Pregius IP Core supports these sensors, it is able to read their data as well as controlling them. It is delivered as a reference design along with an FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.
The functionality of the IP core is conﬁgured either by parameters at compile time, or by Control Registers using an AXI-Lite interface at run time. A C software library conﬁgures the sensor and the IP core.
The SubLVDS Receiver and Deserializer block is connected to the sensor’s output pins and uses the FPGA IO cells to deserialize the image stream. This block is highly FPGA dependent and currently limited to Xilinx FPGAs. The parallel video stream can be cropped and is presented in a Camera Link-like format for further processing.
The IP core is delivered with a full reference design, including an FMC (FPGA Mezzanine Card), which forms the interface between the sensor and a standard FPGA evaluation board. The FMC module is FMC-LPC compliant and does all power and level adaptations required by the IMX CMOS sensor.
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